1. Field of the Invention
The present invention relates to the field of digital computation and more particularly to sequential logic used to multiply two serial numbers to obtain a serial output, the product reflecting the sign of the multiplicand. The invention also relates to a method by which a single precision product may be efficiently obtained. The invention utilizes logic functions particularly adapted to large scale integration.
2. Description of the Prior Art
Multiplication of two binary numbers of m and n bits typically produces a product of (m + n) bits. Assuming that "m" and "n" are equal, the product is of 2m (or 2n) bits and is said to be of double precision. Since in the common case, the digits of the operands are available only to the extent enumerated, the least significant half of the bits forming the product may not be useful, possibly falling within the range of quantization (or other) error present in the operands. In cases where serial operands and serial products are concerned, the time and/or equipment required for producing the double precision product, and then rounding back down to a reasonable word length, may be impractical.
The serial format is particularly attractive in many computation systems, as where the number of input and output terminals is limited, and it is efficiently implemented in metal oxide semiconductor integrated circuit format. Also, typical signal and data processing requires the capability of handling sign and magnitude information. Two's complement notation is one of several known formats for signed arithmetic processing.
In a paper entitled "An Approach to the Implementation of Digital Filters", IEEE Transactions on Audio and Electroacoustics, September 1968, a single precision multiplication apparatus is described wherein the inputs and outputs are serial but in which the operands must be positive. In a second paper by Sypherd, "Design of Digital Filters Using Read-Only Memories", Proceedings of the National Electronics Conference, 1969, a serial-parallel multiplication apparatus is described using a read only memory for summation of partial products.
The implementation of certain logic functions in a manner suitable for large scale integration in MOS technology is treated in a book entitled MOS Integrated Circuits edited by William M. Penney and Lillian Lau, Van Nostrand Reinhold Company, New York 1972.